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Wherein the OS and user get more control over the L1,L2 and L3 caches, mostly for performance. Traditionally, the L1, L2 and L3 SRAM caches are meant to be managed solely by the CPU. After all, from the perspective of the user’s program, the abstraction available for non-persistent data is that of memory; caches are there purely for performance. They could be managed by the user or even the OS, but from ‘What Every Programmer Should Know About Memory’ by Ulrich Drepper: … the gains of having f...