EfficientNet-EdgeTPU: Creating Accelerator-Optimized Neural Networks with AutoML

1 · Google AI Research · Aug. 6, 2019, 5:19 p.m.
Posted by Suyog Gupta, Machine Learning Accelerator Architect and Mingxing Tan, Software Engineer, Google Research For several decades, computer processors have doubled their performance every couple of years by reducing the size of the transistors inside each chip, as described by Moore’s Law. As reducing transistor size becomes more and more difficult, there is a renewed focus in the industry on developing domain-specific architectures — such as hardware accelerators — to continue advancing co...